Standard ratio, and possible PMOS and NMOS width

Standard Cell Library

Standard cells are designed based on power, performance and
area. Cell architecture is deciding by cell height which is based on pitch. The
track, pitch, ? ratio, and possible PMOS and NMOS width constant for particular
library.

We Will Write a Custom Essay Specifically
For You For Only $13.90/page!


order now

Pitch is the distance between two tracks.

               Pitch=21/2(Metal
width) + Via overhead +Metal-to-metal spacing

Standard Height = Pitch * (M-1)

               Where M
represents the number of tracks.

? is the ration between the PMOS width and NMOS width.
Standard cell library contains cells of threshold devices (eg- Standard Vt and
Hight Vt) and different drive strength (multiple fingering).

Different category of
Cells in universal Library

1.     
Basic gated (AND, OR, NOT, NAND, NOR, XOR, XNOR)

2.     
Half Adder and Full Adder

3.     
MUX

4.     
AOI (AND-OR-INV)

5.     
OAI (OR-AND-INV)

6.     
Clock gate

7.     
Metal Ecoable cells

8.     
Tie Cells

9.     
Flops (D Flip flop and Scan-able flop with
set/reset)

10.  
Spare Cells (Fillers, Tap cells, Decaps.. etc)

11.  
Boolean functional cells

12.  
Power management cells (Isolation cell, Level
Shifter, Power gate/switch)

 

Spare Cells

Tap cells

        These
cells are used to provide substrate connection and avoid latch-up. The cells
used to connect n-well to VDD and p-substrate top VSS.

ECO Cells

               The
filler cells which are converted to attain any functionality are called metal
ECO cells. The size of these cells is more as compared to normal cells of same
functionality.

Filler Cells

               These
cells are used to provide power rail continuity. This cells also contain p
substrate and n-well.

 

Decoupling Capacitor
Cells (Decap cells)

               These cap
used in design between power and ground rails. These cells behaves like a
battery when drops present in power rail and maintain the voltage across rails.
These cells aids IR drop issue and removes glitches in power.

End cap cells

               They are
added near the end of rows to terminate the rows properly.

Tie Cell

               There
are 2 type of TIE cell:- TIE High (give output VDD) & TIE Low (give output
VSS).

In design some cell input require a
logic 0 or logic 1 value. Rather than providing connection to VDD/VSS rails,
you connect them to TIE cells. Tie cells are used to avoid direct connection to
power rails to protect cell from damage.